Semiconductor devices generally include multiple film layers. Often, differing material properties of the separate film layers generate stress in the semiconductor device, which may lead to a decrease in performance or even failure of the device. One form of stress in semiconductor devices is generated when film layers that are placed adjacent to one another have different thermal coefficients. In such a case, as the ambient temperature changes, one film layer may expand and/or contract more than an adjacent layer, thereby causing undesirable cracking, buckling, wafer bowing, or piezo-electric effects in the semiconductor device.
FIG. 1 shows a conventional semiconductor device 10 including a substrate 12, a dielectric crossover layer 14, and an encapsulation layer 16. The substrate 12 includes a first surface 18, which is used to support and connect one or more electrical components (not shown). The dielectric crossover layer 14 is located between the first surface 18 of the substrate 12 and the encapsulation layer 16. The dielectric crossover layer includes a dielectric surface 20, which is used to support a number of crossovers 22, such as a first crossover 22A and a second crossover 22B.
The first crossover 22A may include the dielectric crossover layer 14, a first conductive trace 24, and a second conductive trace 26. The second crossover 22B may include the dielectric crossover layer 14, the second conductive trace 26, and a third conductive trace 28. In the first crossover 22A, the first conductive trace 24 may be a crossover trace, while the second conductive trace 26 may be a surface trace, such that the first conductive trace 24 crosses over the second conductive trace 26 on the dielectric surface 20 of the dielectric crossover layer 14. In the second crossover 22B, the second conductive trace 26 may be a crossover trace, while the third conductive trace 28 may be a surface trace, such that the second conductive trace 26 crosses over the third conductive trace 28 on the dielectric surface 20 of the dielectric crossover layer 14. The solid lines shown in FIG. 1 represent the portion of the first conductive trace 24 and the second conductive trace 26 located on the dielectric surface 20 of the dielectric crossover layer 14, while the dotted lines represent the portions of the first conductive trace 24, the second conductive trace 26, and the third conductive trace 28 located below the dielectric surface 20 of the dielectric crossover layer 14.
FIG. 2 shows details of the first crossover 22A, which includes a portion of the dielectric crossover layer 14, the first conductive trace 24, and the second conductive trace 26. As discussed above, the first conductive trace 24 is a crossover trace, which crosses over the second conductive trace 26 on the dielectric surface 20 of the dielectric crossover layer 14, while the second conductive trace 26 is a surface trace, which runs under the first conductive trace 24 on the first surface 18 of the substrate 12. Specifically, the first conductive trace 24 is partially disposed on the first surface 18 of the substrate 12 and the dielectric surface 20 of the dielectric crossover layer 14, such that the first conductive trace 24 crosses over the second conductive trace 26 on the dielectric surface 20. Notably, the dielectric crossover layer 14, which separates the first conductive trace 24 and the second conductive trace 26 to prevent contact between the two, is a blanket layer that substantially extends over the periphery of the first surface 18 of the substrate 12. Accordingly, the solid lines shown in FIG. 2 represent the portion of the first conductive trace 24 located on the dielectric surface 20 of the dielectric crossover layer 14, while the dotted lines represent the portions of the first conductive trace 24 and the second conductive trace 26 located below the dielectric surface 20 of the dielectric crossover layer 14.
Although effective at supporting the first crossover 22A and the second crossover 22B in the conventional semiconductor device 10, the dielectric crossover layer 14 often generates stress in the semiconductor device. This may be, for example, due to the fact that the dielectric crossover layer 14 and the encapsulation layer 16 are blanket layers that often have divergent thermal coefficients. As discussed above, the dielectric crossover layer 14 or the encapsulation layer 16 may thus expand and/or contract more than the other, thereby leading to undesirable cracking, buckling, wafer bowing, or piezo-electric effects in the semiconductor device which may lead to a decrease in performance or even failure of the device.
As feature sizes in semiconductor devices decrease and wafer sizes increase, stress in the semiconductor device becomes increasingly problematic. Accordingly, there is a need for a semiconductor device with reduced stress between the film layers therein.